EDN

Cadence SystemVerilog pledge may ease language split

SANTA CRUZ, Calif. — Fears of a Verilog language schism may ease this week as Cadence Design Systems announces that it plans to support “aspects” of Accellera's SystemVerilog 3.1 language. Cadence's ...
Design-Reuse

SystemVerilog key to new design paradigm

SAN JOSE, Calif. — The SystemVerilog 3.1 specification is undergoing final reviews and Synopsys plans to have a synthesis tool for SystemVerilog assertions in the next 12 months, said Synopsys CEO ...
EDN

SystemVerilog assertions unify design and verification

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...
Electronics Weekly

Partner programme promotes SystemVerilog language

Synopsys has set up a partner programme to help promote the SystemVerilog design language and improve the interoperation of tools. The SystemVerilog Catalyst Programme is open to EDA tool vendors, ...
Electronics Weekly

Mentor and Synopsys give support to SystemVerilog design language

Mentor and Synopsys are putting their weight behind SystemVerilog, a nextgeneration hardware description language that extends Verilog to supportabstract behavioural design. What Cadence thinks of ...
Business Wire

Verific Ships First Commercially Available SystemVerilog Parser

Verific Design Automation, the leading provider of Verilog and VHDL front ends for electronic design automation (EDA) applications, today announced that it is shipping the first commercially available ...
Design-Reuse

SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology

The growing complexity of SoCs and the reduced life cycle of electronic products demand higher levels of design productivity while meeting compressed development schedules. The reuse of design IP ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

"VeriEZ is strongly committed to supporting technologies that enable wide-spread adoption of the SystemVerilog language. The Advanced Verification Methodology (AVM) is sure to add tremendous value to ...
Electronic Design

Writing Testbenches Using SystemVerilog

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking ...
Electronic Design

First Commercial Parser Ships For System Verilog

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial ...