Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...

Of all the electronic design automation (EDA) tools on the market, design for test (DFT) may be the most under-appreciated; even though building testability into a chip during the design phase will ...

As the demand for processing power for artificial intelligence (AI) applications grows, semiconductor companies are racing to develop AI-specific silicon. The AI market is incredibly dynamic, with ...

Design-for-test (DFT) is essential to ensure that complex designs can be thoroughly tested. Testing demands continue to increase as designs grow in gate count and fabrication process technologies ...

It is often said that the emergence of the System-on-Chip will require fundamental changes in the approaches to design for testability (DFT.) These changes, it has been suggested, will take the form ...

SUNNYVALE, Calif., June 9, 2020 — Real Intent, Inc., today announced Verix DFT, a full-chip, multimode DFT static sign-off tool. Verix DFT’s comprehensive set of fine-grained DFT rules help designers ...

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, ...

This paper describes how using a smarter DFT infrastructure and automation can greatly improve the DFT schedule. A structural DFT infrastructure based on plug-and-play principles is used to enable ...

With any new SoC project, there are more things to go wrong than ever imagined during the optimistic early phase of defining the product, writes Ron Press, of Mentor, a Siemens Business. However, the ...

The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.